How do I convert from package to die ?

Introduction

For some years, the most common method for assembling electronic circuit boards has been to “Solder” pre-screened packaged devices onto organic laminates. For complex systems with large numbers of components, final test yield has been the main cost driver and fault diagnosis and rework can prove to be prohibitively expensive, when compared with the small additional cost of packaging and screening, prior to assembly. The package serves two purposes. Firstly, to convert the die into a form in which it can be adequately screened and secondly, to protect the die from environmental damage. Continued investment at wafer fabrication has both dramatically improved yield and reduced costs of unpackaged die. At the same time, die size reductions, coupled with increased pin counts have resulted in the cost of the package assembly once again being a major part of overall system cost. For ultra low-cost systems, unpackaged die are often used. These systems usually only have few active components and material costs are low enough for any electrical test failures to be discarded. High-end systems may also use bare die, where conventional packaging might result in unacceptable levels of degradation in electrical, mechanical or thermal performance. This tutorial is intended to give some basic guidance in the use of unpackaged and minimally packaged die.

Suitable Assembly Methods

The following are suitable assembly methods for using bare die: Flip Chip-Csp

The Chip-Scale-Package is a minimum surface area packaging technology, which comprises a laminate interposer that converts the connections on the die to a standard surface mount footprint, suitable for solder attachment. The die may be electrically connected to the laminate, using either standard wire bonding or flip-chip and particularly in the case of wire bonded parts, the parts may also be encapsulated using a liquid encapsulant (glob-top) or thermosetting epoxy (transfer moulded).

CSP is a high volume process, offered by most of the major assembly foundries and currently is the lowest cost package option at around $0.02/per pin. Mintech can offer a prototyping service, with NRE around $5k. Otherwise assembly houses require volumes in excess of 10K units. Some devices are available in CSP, fully tested and screened, from the original die fabricators.

Solder Flip Chip

Some devices are also available, from the original fabricators, with solder bump connections on top of the bond pads. The process is performed at wafer level as an extension to the wafer fabrication process. The entire bonding pad window is totally encapsulated by a barrier layer, then sputtered, or plated, with nickel followed by a sacrificial gold coating to preserve solderability. Various composition solder bumps are then reflowed onto the surface.

Where the devices are not directly available from the original supplier, sub-contract bumping is available. There is usually an NRE of around $10K, for masks, and costs per bump range from $0.005/bump in very high volumes to $0.2/bump for less than 10 wafers. Gold-Bump Flip Chip

Gold bumping is by far the most flexible process.

The bumps are applied using a standard gold-thermosonic wire bonder. We can bump individual die or whole wafers, there is usually no NRE and we can control the profile of individual bumps, to form anything from a flat disc up to a tall thin post. We have a range of wires from 18µm up to 125µm and have successfully handled pitches down to 60µm.

Although gold bumps can be attached with solder, there are also a wide range of other attachment processes that can be used, including thermo-compression and Z-axis conductive (anisotropic) adhesive.

Costs for bumping are less than for standard wire bonding, which is still the leading method of interconnect and used in most of the standard plastic packages. Latest generation bonders boast over 25 bumps/second. Thermosonic gold bumping will ultimately be more expensive than wafer level bumping processes, (one supplier estimated the cut-off at over 100K wafers).

Flip Chip Conversion

The conversion can be performed all at once or in stages. However "flipping" some of the die and not others can cause havoc with the routing of the interconnect and as a result, the potential saving in board area may not be realised. Gold-bump flip, with Z-axis adhesive attach, is usually the best approach, as it can be achieved using standard surface mount equipment. The biggest draw back is that gold bump uses standard wire bond pads, so the pitch between connections may be as little as 100µm. On some designs, the tracks on the pcb may need to be 30µm wide in places.

To use standard wire bond Chip-on-Board, all of the solder components need to be attached first and the board thoroughly cleaned. The die are then attached, with adhesive prior to wire-bonding. This requires additional investment for the die attach and wire bonding equipment. For devices with less than 40 pins 5mil line and space will be adequate for wire bonding. Larger die may need power/gnd rings and multi-tier bonding to maintain useable wire lengths (<5mm).

Solder flip can be used if the devices are available direct from the wafer fabricator. Otherwise, the initial outlay for both wafers and NRE will be prohibitive (and not recoverable if the system does not work). Currently, solder bump pitches will be >200µm and 4mil line and space can be used to connect between devices.

The first step is always to get the die sizes and pad co-ordinates and produce a trial layout using your suppliers pcb design rules. NB. Areas for wire bonding need to be plated with minimum 3.5µm nickel and 0.35µm gold and where wires cross, the tracks need to be covered with solder resist. Then get the assembly house (or Mintech) to verify that the assembly meets their rules.

It is advisable to run off a small batch of boards and arrange to have a few prototypes assembled and tested, before buying large volumes.

When buying un-bumped die, they must be stored in vacuum or dry nitrogen until ready to use.

Solder bump is not likely to prove competitive up to 100K wafers, due to high NRE. Gold bump starts at $0.05 per bump and decreases to less than $0.01 per bump at 100K wafers.

Chip On Board

Chip on board solutions offer higher density than traditional packaged components. By eliminating traditional packages and using die it is also possible to improve density, enhance reliability and improve speed all of which fit with Mintech Interconnect and Test philosophy of offering packaging solutions. Further advantages of Chip on Board technology are faster time to market, low tooling costs and system upgrade flexibility. Mintech Interconnect and Test have many years experience of Chip on Board technology and are leaders in implementation of the technology to provide solutions. Typical products produced to date include memory modules and mixed technology HDP (High Density Packaging) solutions.

Mintech Chip on board technology may be applied to a range of substrate types including:

• FR4 / FR5
• BT Resin
• PTFE
• Flex
• HTCC & LTCC

Die attach is usually achieved using silver loaded epoxy adhesive. Either Gold or Aluminium wire bond may be employed and die may be mechanically protected with either rigid or semi-rigid glob coating.

Die Handling

Bare die are very easily damaged. Unlike packaged parts, which may still be recoverable after mishandling, bare die will be rendered totally unusable by even the slightest mechanical damage. They are also very susceptible to chemical attack and surface contamination. They must be kept clean and dry, preferably in vacuum or inert atmosphere, until ready for use. Bare die should never be allowed to come into contact with the skin, or any object that may have been in contact with it. Perspiration, natural oils, hand cream and cosmetics are all both corrosive and electrically conductive and once the part has been contaminated, no amount of cleaning will restore the original performance and reliability. Most common die have a top passivation layer, which provides some protection for the delicate structures beneath and so can be transported and placed in position using soft-tipped, vacuum, pick-up tools. Many discrete devices (transistors and diodes), MEMMs and microwave devices have no surface protection. Some can be handled with soft pick-ups and others can only be handled using tools that locate on the sides. Even on passivated die, the bond pads that make the electrical connections are exposed and susceptible to chemical attack. All semiconductor devices, whether packaged or unpackaged, may be inadvertently damaged by static discharges. These charges can build up on any insulating surface, including the operator’s hair and clothing and are measured in tens of thousands of volts. Just touching any of the connections on an earthed component can induce tunnelling defects in the internal dielectric layers. The best way to avoid this is to ensure that all operators, tools and equipment are suitably earthed, before any contact is made.

Assembly Flow

There are two competing technologies for direct die attach - Flip-Chip and Chip-On-Board. The flip-chip assembly flow is very similar to that used for surface mount reflow soldering and, in many instances, existing equipment can be used. Chip-On-Board requires an additional piece of equipment, to make the connections between the die and the rest of the circuit, known as a “Wire bonder”. Ideally the board should be designed so that any soldered components can be attached first. The preferred assembly sequence is as follows. 1) Reflow solder all passives and packaged devices. 2) Thoroughly clean to remove all flux residues. 3) Solder attach flip chip and metal-backed die using a heated pick-up tool or reflow in Nitrogen. 4) Apply adhesives. 5) Die Attach 6) Wire Bond 7) Encapsulate/Underfill, fit heat-sinks and covers Where there are no soldered components, passives and metal-backed die may also be attached with conductive adhesive to simplify the flow.

Flip-Chip

There are numerous methods for creating flip-chip die. The most prevalent are solder bump (also known as C4) and stud bump. The solder bumped parts can generally be treated just like very small Ball Grid Arrays. The pitch between the balls is much smaller than standard BGA packages, usually 0.2 to 0.25mm. Most devices actually have bond pad pitches much smaller than 0.2mm and in order to use solder balls, additional layers need to be created on top of the die to “redistribute” fine pitch peripheral connections into a coarser pitched array that covers the whole surface. The solder balls processes need to be performed at wafer level and can often prove to be more expensive than conventional packaging. The stud bump process can be performed on singulated die, as well as wafers. After the conventional thermosonic ball bond is made onto die, the wire is broken off at the top of the flattened ball, without making a second connection. (See Figure 1.) Having “bumped” all of the pads, the die can be attached to the board using many different techniques. The most popular technique is to use electrically conductive adhesives. These materials can be screen printed, or pneumatically dispensed, in the same way as solder pastes. They also have additional benefits in that the joints between the die and the board can be made at lower temperatures than solders, they do not need to contain potentially corrosive fluxes, and are completely “Lead-Free”. Other methods for attaching bumped die include anisotrophic and non-conductive adhesives; ultrasonic, thermosonic and thermocompression bonding; and various solders.

Figure 1. Stud Bumped die

Bare Die Attachment

In most Chip-on-Board applications, the die is also attached using silver-loaded epoxy. Not all of these materials can guarantee, over time, a reliable low resistance connection to bare silicon. So caution should be exercised when selecting materials for attaching transistors and diodes. Power transistors and other die that dissipate large amounts of heat, or require extremely low electrical resistance between the back of the die and the board, usually have gold or silver deposited on the underside. These parts can be attached using a variety of solder alloys, provided that the solder layer is reasonably homogenous. If the layer is too thin the mismatch in coefficient of thermal expansion between the die and board may cause either the joint or the die to crack. If, on the other hand, the layer is too thick, or contains pockets of trapped air or flux, the thermal resistance will be higher and the die could easily overheat and fail during operation. For this reason, placing these die into wet solder paste is not recommended. The flux and organic solvents, within solder paste, may also induce corrosion or create leakage currents, if allowed to contact the upper surface of the die. Conventional thermo-setting epoxies are also not recommended for high-power devices. Firstly, epoxies are very hard, stiff materials, which will increase the risk of die cracking and secondly both the electrical and thermal resistance of even the best silver filled epoxies is still over 20 times higher than most solders. There are some soft thermoplastic conductive films, which can be suitable for many devices, but even these are not generally recommended for power dissipations greater than 10W.

Tab Mounting

Many of the older transistors and diodes either do not have any metal backing, or alternatively just have a thin flash of gold. If a suitable conductive epoxy cannot be found, one alternative is to first eutectic (99Au/1Si) bond the die onto a small gold plated metal plate (tab), which can then either be soldered onto the circuit board, or attached with adhesive and if necessary apply jumper wires to reinforce the electrical path. (See Figure 2.) It is not possible to eutectic bond bare-backed die directly onto most conventional boards as the melting point for gold-silicon is around 370～C.

Figure 2. Tab mounted die construction.

Gold Thermosonic Wire Bonding

By far the most common technique for making electrical connections between the top of the die and board is gold thermosonic wire bonding. Again this is the same process as is used in the majority of plastic packages. A fine gold wire is fed through a hole in a ceramic capillary and a high voltage applied to the exposed end, causing it to roll back into a ball. The ball is pressed against the connection point on the die (bond pad) and ultrasonic energy applied to create a bond. The capillary is then raised and moved to just above the second bond position on the board. The wire is then pressed against the second bond pad and again ultrasonic energy is applied, which simultaneously bonds the wire to the board and partially saws though it. When the capillary is raised the wire protruding from it breaks at the second bond position, leaving a short tail beneath the tip of the capillary, which can then be formed into the next ball. In order for this process to work, the bond pad on the board needs to coated with a nickel barrier layer finished either aluminium or gold. Gold to gold bonds can be made at room temperature, but to bond gold to aluminium the temperature needs to be increased to around 100～C. It is also possible to make gold bonds to silver plated boards. However, the surface will oxidise rapidly and some form of pre-treatment (e.g. Plasma Etch) may be required if the boards have not been correctly stored, prior to use. Gold-aluminium bonds have limited life at elevated temperatures. Above 75～C, the aluminium bond pads will continue to dissolve into the gold and the bonds will first start to exhibit increased electrical resistance and then eventually fail. The rate of dissolution increases exponentially with temperature and at 175～C, failures will occur in less than a month.

Wedge Bonding

For standard devices (i.e. those with aluminium bond pads), which may be routinely required to operate at elevated junction temperatures, aluminium wire should be used. It is possible to use aluminium wire for ball bonding. But, as aluminium will readily oxidise, an inert atmosphere is necessary during the formation of the ball. This can be accomplished by fitting the bonder with an argon gas-shroud. It is, however, far more common to dispense with the ball and use wedge bonding. Instead of feeding the wire vertically through the centre of a ceramic capillary, the wire is fed at a low angle through the back, and under the front edge, of a wedgeshaped, tungsten tool. Pressure and ultrasonic energy are applied, at room temperature, to bond the wire onto the die. The tool then moves to the second bond position and the process repeated. The tool then “steps-back”, to locate an undisturbed portion of wire beneath the foot, before breaking the wire at the second bond. This process is somewhat slower than ball bonding. When ball bonding the second bond can be formed at any part of the circular capillary. So, bonds can be made at any angle. When wedge bonding, the wire can only be fed out in one direction and either the work surface or whole bonding mechanism needs to rotate. Many of the older generation die are suitable for either bonding method, but many newer devices have only been designed for gold ball bonding. As a result, the aluminium on the bond pads may be thinner and there may also be fragile structures immediately beneath the bond site that will be destroyed by the increased loading and ultrasonic vibration associated with aluminium wedge bonding. This is particularly true of Gallium Arsenide die. Some devices are so fragile that even gold thermosonic bonding may induce failure and so gold thermocompression wedge bonding is used. Without the assistance of the ultra-sonic energy, the temperature at the bond site, during thermocompression bonding needs to be higher than 300～C. For high current handling, flat ribbons can also be used.

Underfills

Irrespective of which technique has been used to attach them, the surface of the die will need to be protected against mechanical damage and environmental corrosion. For flip-chips, the stresses induced by CTE mismatch can result in premature failure if there is insufficient clearance between the die. So “Underfills” are recommended for additional mechanical support on flip chip devices. Additionally, leaving an air gap under the die will eventually result in the ingress of atmospheric moisture and other contaminants that can outgas at elevated temperatures, freeze at low temperatures and induce corrosion. Which underfill is used depends on the size of the die, separation between die and substrate and spacing between the connections. The most widely used process is to apply the material at one edge of the die and allow capillary action to draw the underfill under the die and out the other side. Sometimes the connections at the edge of the die are so close together that they act as a dam and the underfill cannot get through. For peripherally connected die, non-conductive adhesive can be applied in the centre of the die attach area prior to placement. For full area arrays, a film adhesive may need to be applied at the wafer level.

Encapsulation

When using wire bonded die, the fine wires need to be protected from mechanical damage. For low-cost room temperature systems a simple cap may be used, which is clipped, or is glued, onto the board. Liquid encapsulant (glob-top) may also be used either on each die or totally encapsulating the whole board. Liquid encapsulants need to have fairly low viscosities, to ensure good coverage of the die and wires, and may need to be contained to stop the material draining away or contaminating other areas on the board. To prevent this a dam of a higher viscosity compatible material is first created around the die area. This also results in a much flatter profile, which is better for coding and fixing external heat sinks. Even flip chip die can benefit from encapsulation, to avoid the potential for cracking of the die, due to flexing or mechanical impact. And for the optimum thermal management a heat-spreader may also be attached. (See Figure 3).

Equipment and Facilities

It is not necessary to have super-clean rooms to perform either chip-on-board or flip chip assembly. Solder flip-chip devices can usually be assembled on a standard SMT line. The main hazard for chip-on-board assembly is yield rather than reliability. Fine particles can block capillaries and screen-printing stencils, produce misalignment, and cause short circuits and scratches. Class 10,000 conditions should be perfectly adequate, for most chip-on-board operations and if problems do occur in particular areas, lamina flow cabinets and hoods can be used to further reduce local particle counts.

Full ESD precautions must be observed at all times. Bare die are notoriously easy to damage, by even comparatively low voltages. In the case of Field Effect Devices, even a few volts can cause failures. Screen-printing is probably the fastest and most controlled method for dispensing adhesives. However, it can only be used on flat boards, when no other components are present Otherwise, adhesives can be applied using pneumatic dispensers. Placement accuracy is not so important for chip-on board, as the bond wires can vary in length to accommodate, and many parts can be placed using suitable hand held tools, working under a low power microscope. Maximum displacement for flip chips is related to the distance between the bumps, which in some cases might be less than 10 microns. So, precision pick and place equipment must be used. All ovens used for soldering and curing adhesives should be fan assisted and suitably vented. For maximum throughput, conveyor type systems should be used. Heath and safety information will be available from the relevant material suppliers. For die with only a few wires manual wire bonders are best, since the time to bond the wires will be less than the time taken to enter reference coordinates. Above ten wires per board, automatic wire bonders will prove far more cost effective in the long term. For quality control purposes it is also worth investing in a pull/shear tester, to check the adhesion of the die and bond wires.